Power management techniques for electronic systems are becoming increasingly important. Memory devices, such as flash memory devices and DRAM devices, consume a significant portion of the overall power consumed by various electronic systems. In the prior art, most power management techniques for memory devices involved changing the frequency of one or more clocks received or used by the memory device. In general, decreasing a clock frequency generally will result in less power consumption.
However, certain portions of a memory device, such as a sense amplifier used to read data from a memory array, will consume the same level of power regardless of any changes in clock speed. This is inefficient because prior art sense amplifiers often are designed to achieve the highest performance possible at the highest possible clock speed. In instances where a lower clock frequency is used, as might be the case in a prior art power saving mode, the sense amplifier will be operating at an unnecessarily high performance level.
What is needed is an improved method and apparatus for performing power management in a memory device where the incoming clock frequency is detected and the memory device's operation and power consumption is altered based on the clock frequency.